
PIC16(L)F1825/1829
DS41440C-page 338
2010-2012 Microchip Technology Inc.
BCF
Bit Clear f
Syntax:
[ label ] BCF
f,b
Operands:
0
f 127
0
b 7
Operation:
0 (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
BRA
Relative Branch
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Operands:
-256
label - PC + 1 255
-256
k 255
Operation:
(PC) + 1 + k
PC
Status Affected:
None
Description:
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion. This branch has a limited range.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W)
PC
Status Affected:
None
Description:
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
BSF
Bit Set f
Syntax:
[ label ] BSF
f,b
Operands:
0
f 127
0
b 7
Operation:
1 (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0
f 127
0
b 7
Operation:
skip if (f<b>) = 0
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
Operands:
0
f 127
0
b < 7
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.